FPGA Implementation of Modular Exponentiation for RSA Cryptosystem

In this paper, the implementation of RSA (Rivest, Shamir and Adleman) cryptosystem using Hardware/Software (HW/SW) co-design approach is presented. The main function of RSA is the Modular Exponentiation (ME) which is accomplished by repeated Modular Multiplications (MM’s) on large integers. In this work, we propose the implementation of the ME as a Programmable System on Chip (PSoC), using the soft processor core MicroBlaze of Xilinx. In the proposed embedded system, the control of the ME algorithm is executed by the embedded processor, while the MM’s are computed within specific hardware. Because, the MM is usually considered as timeconsuming, the Montgomery modular multiplication algorithm is employed to realize our accelerator customized IP (Intellectual Property). The results show that the application to RSA 1024bits, the execution time of the ME is about 15.14 ms Keywords— RSA, Montgomery Modular Multiplication, FPGA, PSoC.